The present invention generally relates to fabrication methods and resulting structures for semiconductor devices. More specifically, the present invention relates to laser spike annealing (LSA) for solid phase epitaxy (SPE) and low contact resistance in an SRAM with a shared pFET and nFET trench.
In contemporary semiconductor device fabrication processes a large number of semiconductor devices such as field effect transistors (FETs) are fabricated on a single wafer. Some non-planar device architectures, such as fin field effect transistors (finFETs) and finFET-based static random-access memory (SRAM), employ semiconductor fins and gates that can be contacted outside the active region, resulting in increased device density and some increased performance over lateral devices. A typical finFET device includes a fin that extends upward from the substrate. The gate can be formed over and around a portion of the fin. The portion of the fin that is under the gate defines the channel region of the transistor. The portions of the fin that are not under the gate form the source region and the drain region, respectively.